The present invention relates to a decoder circuit of a semiconductor memory device.
A fundamental decoder circuit of a semiconductor memory device is illustrated in FIG. 1A. The decoder circuit of FIG. 1A comprises address input terminals 1 (A.sub.0, A.sub.1, A.sub.2, . . . ), address buffers 21, 22, 23 . . . , decoder lines 3 (d.sub.0, d.sub.0, d.sub.1, d.sub.1, . . . d.sub.n, d.sub.n), word drivers 41, 42, 43, . . . and word lines 5 (W.sub.0, W.sub.1, W.sub.2, . . . ). Memory cells are connected to cross points of the word lines and bit lines, though the memory cells and the bit lines are not shown in FIG. 1A. An emitter follower connection transistor Q.sub.E is included in the address buffer. In the circuit of FIG. 1A, constant current sources S.sub.1, S.sub.2 and S.sub.3 are provided in the address buffers, the decoder lines and the word drivers, respectively. Currents I.sub.1, I.sub.2 and I.sub.3 pass through the constant current sources S.sub.1, S.sub.2 and S.sub.3, respectively. Each of these constant current sources consists of, for example, one of the circuits (1), (2) and (3) illustrated in FIG. 1B. The number of the input terminals A.sub.0, A.sub.1, A.sub.2, . . . is N. The number of the address buffers 21, 22, 23, . . . is also N. The number of the decoder lines d.sub.0, d.sub.0, d.sub.1,d.sub.1, . . . is 2N. The number of the word drivers 41, 42, 43, . . . and accordingly the number of the word lines W.sub.0, W.sub.1, W.sub.2, . . . is 2.sup.N.
Accordingly, in the circuit of FIG. 1A, the numbers of the constant current sources S.sub.1, S.sub.2 and S.sub.3 are N, 2N and 2.sup.N, respectively, so that the number of the entire constant current sources is equal to "N+2N+2.sup.N ". The total current I' which passes through the entire constant current sources is "I'=NI.sub.1 +2NI.sub.2 +2.sup.N I.sub.3 ", if the constant current sources S.sub.1, S.sub.2 and S.sub.3 consist of the circuits illustrated in FIG. 1B which are operated in the normally-on manner. Accordingly, the value of the total current I' becomes greater if the number of the input terminals N is increased.
A prior art decoder circuit of a semiconductor circuit, which avoids the above described increase of the number of the constant current sources and the value of the total current, is illustrated in FIG. 2. The decoder circuit of FIG. 2 comprises address input terminals A.sub.0, A.sub.1, A.sub.2 . . . , address buffers 21, 22, 23, . . . , decoder lines 3(d.sub.0, d.sub.0, d.sub.1, d.sub.1 . . . d.sub.n, d.sub.n), word drivers 41', 42', 43', . . . and word lines W.sub.0, W.sub.1, W.sub.2, . . . . In the circuit of FIG. 2, no constant current sources are provided in the decoder lines and the word drivers, and the constant current sources are provided only in the address buffers.
If the word line W.sub.0 connected to the word driver 41' is selected, every one of the diodes D.sub.1, D.sub.2, . . . connected to the decoder lines is in an OFF state, thus the transistor Q.sub.W is in an ON state, and accordingly the word line W.sub.0 is in a HIGH level. On the contrary, if the word line W.sub.0 connected to the word driver 41' is not selected, at least one of the diodes D.sub.1, D.sub.2, . . . connected to the decoder lines is in an ON state, thus the transistor Q.sub.W is in an OFF state, and accordingly the word line W.sub.0 is in a LOW level. A diode connected to a decoder line in a HIGH level is in an OFF state, while a diode connected to a decoder line in a LOW level is in an ON state. An input signal A.sub.0 is compared with a reference signal E.sub.S in the address buffer 21. When the input signal A.sub.0 is higher than the reference signal E.sub.S, an output signal A.sub.D of the address buffer is in a LOW level, so that the decoder line d.sub.0 is in a LOW level. On the contrary, when the input signal A.sub.0 is lower than the reference signal E.sub.S, an output signal A.sub.D of the address buffer is in a HIGH level.
In the circuit of FIG. 2, the number of the constant current sources is only N. Assuming that the value of the current passing through the resistor R.sub.0 of the word driver 41' of FIG. 2 is equal to the value of the current I.sub.3 passing through the constant current source S.sub.3 of the word driver 41 of FIG. 1A and that the value of the current passing through a load resistance of the address buffer 21 of FIG. 2 is negligible, the total current I" which passes through the constant current sources is only "I.sub.c =NI.sub.1 +2(2.sup.N -1)I.sub.3 ". This value of the total current I" is considerably smaller than the total current I' of the circuit of FIG. 1A.
However, in the circuit of FIG. 2, the raising of the potential of a decoder line to a HIGH level is effected by charging up the decoder line, which has a great capacitance C.sub.d, through the resistor R.sub.l of the address buffer. Because of the great value of the time constant R.sub.l C.sub.d, a considerable length of time is required to build up the potential of the decoder line when a signal is applied to an address input terminal, so that the speed of response of the decoder line to the input signal is reduced.
The prior art decoder circuit of a semiconductor memory device illustrated in FIG. 2 is disclosed in, for example, the U.S. Pat. No. 3,914,620.
The present invention is proposed in order to solve the problems in the above described prior art decoder circuit of a semiconductor memory device.